FIG. 1 is a partial cross-sectional view of an intermediate structure for a semiconductor device 100 having a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) gate stack 102 including a conventional oxide-nitride-oxide (ONO) stack 104 formed over a surface 106 of a semiconductor substrate 108 according to a conventional method. The device 100 typically further includes one or more diffusion regions 110, such as source and drain regions, aligned to the gate stack and separated by a channel region 112. The SONOS gate stack 102 includes a poly-silicon (poly) gate layer 114 formed upon and in contact with the ONO stack 104. The poly gate 114 is separated or electrically isolated from the substrate 108 by the ONO stack 104. The ONO stack 104 generally includes a silicon oxide tunneling layer 116, a silicon nitride charge trapping layer 118 which serves as a charge storing or memory layer for the device 100, and a silicon oxide blocking layer 120 overlying the charge trapping layer 118.
Such SONOS-type transistors are useful for non-volatile memory (NVM). The charge trapping layer stores charge to provide non-volatility. To program (i.e. write to) the n-channel SONOS-type device, a positive voltage is applied to the control gate (Vcg) while the source, body and drain are grounded. An energy band diagram, trapped charge distribution and trap density distribution of a conventional n-channel SONOS device having a channel 212, oxide tunneling layer 216, nitride memory layer 218 and oxide blocking layer 220 during programming is depicted in FIG. 2. As shown, the positive Vcg produces a field across the SONOS stack resulting in some negative charge at the conduction band energy level in the buried channel of silicon substrate channel to undergo Fowler-Nordheim tunneling (FNT) through the tunneling layer and into the charge trapping layer. The electrons are stored in traps having mid gap energy levels in the charge trapping nitride. As illustrated, the trap density distribution is substantially uniform throughout the charge trapping layer. As further shown, under bias, the trapped charge distribution is such that the majority of trapped charge is in the portion of the charge trapping layer (i.e. memory layer) proximate to the blocking oxide. To erase then-channel SONOS device, a negative voltage is applied to the control gate 314. An energy band diagram showing the channel 312, oxide tunneling layer 316, nitride memory layer 318 and oxide blocking layer 320 during erasing is depicted in FIG. 3. As shown, the negative Vcg produces a field across the SONOS stack attracting hole tunneling charge through the tunneling layer and into the charge trapping layer.
SONOS-type devices are gaining in popularity for high density memory applications, such as embedded NVM. It is known in the industry that uniform channel Fowler-Nordheim tunneling (FNT) and/or direct tunneling (DT) for program and erase result in improved reliability over other methods. A combination of FNT and DT is referred to here and is referred to as modified Fowler-Nordheim tunneling (MFNT). Currently, conventional SONOS operate in the 10 V range for MFNT. However, an advantage of SONOS over other NVM devices is voltage scalability. It has been theorized, with proper scaling, there exists potential in SONOS to achieve a memory technology operable in the 5 volt (V) range, rather than the 10 V range of conventional SONOS-type devices or 12 V-15 V range of conventional flash technology. SONOS-type devices operable at low voltages (approaching 5 V) are advantageously compatible with low voltage CMOS. Alternatively, faster programming or erasing may be possible at a particular voltage for a scaled device. However, successful scaling of SONOS-type devices is non-trivial. For example, FIG. 4 depicts programming and erase times for a conventional SONOS device employing a conventional ONO stack comprised of a 10 nm thick silicon dioxide blocking layer, a 7 nm thick silicon nitride charge trapping layer, and a 3 nm thick silicon dioxide tunneling layer. As shown, the programming/erase time increases dramatically when Vcg is scaled down. Generally, program/erase times less than 1 millisecond (ms) are desirable for embedded memory applications. However, such 1 ms program/erase times may be achieved in the conventional SONOS stack only with a Vcg of +/−10 V. Conventional SONOS program/erase times extend to 100 ms or more when Vcg is reduced to approximately +/−9 v.
Furthermore, reducing the programming voltage results in a reduction of the erase or program window (i.e. memory window). This is because the electric field is across the ONO stack is reduced if the equivalent oxide thickness (EOT) of the entire ONO stack is not scaled down as the voltage is reduced. Reducing the EOT of the stack is non-trivial because reducing the tunneling layer thickness to allow the same initial erase level at a lower applied voltage (Vcg) can result in a detrimental increase in the erase and program decay rate Similarly, if the charge trapping layer thickness is reduced, the charge centroid is placed closer to the substrate, increasing charge loss to the substrate. Finally, when the blocking oxide thickness is scaled down, the electron reverse injection from the control gate is increased, causing damage to the ONO stack and data retention loss. Reverse injection is manifested as further shown in FIG. 4, where the FNT erase reaches “saturation.” This occurs when electrons are back streamed from the gate into the memory layer faster than they can be removed via hole transport across the tunnel oxide. Accordingly, there remains a need to scale the ONO stack of a SONOS device in a manner capable of providing a device operable at a lower program/erase voltage.